The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2019

Filed:

Aug. 07, 2017
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Kenjiro Uesugi, Kawasaki, JP;

Toshiki Hikosaka, Kawasaki, JP;

Shinya Nunoue, Ichikawa, JP;

Assignee:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 21/44 (2006.01); H01L 23/532 (2006.01); H01L 23/482 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28273 (2013.01); H01L 21/28008 (2013.01); H01L 21/44 (2013.01); H01L 23/482 (2013.01); H01L 23/53295 (2013.01);
Abstract

According to one embodiment, a semiconductor device includes first, second, and third electrodes, and first, second, third, fourth, and fifth semiconductor regions. The first electrode includes a first conductive region. The second electrode includes a second conductive region separated. The third electrode includes a third conductive region. The first semiconductor region is separated from the first, second, and third conductive regions. The second semiconductor region is provided between the first conductive and semiconductor regions, between the second conductive and first semiconductor regions, and between the third conductive and first semiconductor regions. The third semiconductor region is provided between the first conductive region and the second semiconductor region. The fourth semiconductor region is provided between the second conductive region and the second semiconductor region. The fifth semiconductor region is provided between the third conductive region and the second semiconductor region and between the third and fourth semiconductor regions.


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