The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 2019
Filed:
Jan. 15, 2018
Applicant:
Winbond Electronics Corp., Taichung, TW;
Inventor:
Ying-Te Tu, Kaohsiung, TW;
Assignee:
WINBOND ELECTRONICS CORP., Taichung, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/41 (2006.01); G11C 11/4076 (2006.01); H03K 3/0233 (2006.01); G11C 17/14 (2006.01); G11C 17/16 (2006.01); G11C 29/00 (2006.01); G11C 11/4097 (2006.01); G11C 19/00 (2006.01);
U.S. Cl.
CPC ...
G11C 11/41 (2013.01); G11C 17/143 (2013.01); G11C 17/16 (2013.01); G11C 29/787 (2013.01); H03K 3/02332 (2013.01); G11C 11/4076 (2013.01); G11C 11/4097 (2013.01); G11C 19/00 (2013.01);
Abstract
A fuse array and a memory device are provided in the invention. The fuse array includes a plurality of fuses and a plurality of first D flip-flops. The fuses are configured to generate a plurality of data signals. Each of the first D flip-flops is respectively coupled to one corresponding fuse of the fuses to receive the data signal from the corresponding fuse and the first D flip-flops transmit a clock signal and the data signal to a plurality of second D flip-flops comprised in a plurality of memory cells. The first D flip-flops are connected in series and the second D flip-flops are connected in series.