The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2019

Filed:

Nov. 14, 2014
Applicant:

Cavium, Llc, Santa Clara, CA (US);

Inventors:

Bryan W. Chin, San Diego, CA (US);

Wu Ye, Cupertino, CA (US);

Yoganand Chillarige, Cambridge, MA (US);

Paul G. Scrobohaci, Menlo Park, CA (US);

Scott Lurndal, San Jose, CA (US);

Assignee:

Cavium, LLC, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/26 (2006.01); G06F 1/08 (2006.01); G06F 1/12 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 13/26 (2013.01); G06F 1/08 (2013.01); G06F 1/12 (2013.01); G06F 13/1652 (2013.01); G06F 13/1673 (2013.01);
Abstract

Methods and systems are disclosed for routing and distributing interrupts in a multi-processor computer to various processing elements within the computer. A system for distributing the interrupts may include a plurality of logic devices configured in a hierarchical tree structure that distributes incoming interrupts to interrupt redistributors (redistribution devices). The system also includes plural processing elements, where each processing element has an associated bus address. A shared serial bus couples the redistribution devices and processing elements. Each of the redistribution devices is configured to transfer the incoming interrupts to at least one of the processing elements over the common bus, based on the bus address.


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