The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 2019
Filed:
Dec. 29, 2016
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Wim Heirman, Ghent, BE;
Yves Vandriessche, Kontich, BE;
Assignee:
INTEL CORPORATION, Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/52 (2006.01); G06F 11/30 (2006.01); G06F 1/3228 (2019.01); G06F 12/084 (2016.01); G06F 12/0804 (2016.01); G06F 12/0808 (2016.01); G06F 12/0831 (2016.01); G06F 12/0842 (2016.01);
U.S. Cl.
CPC ...
G06F 11/3037 (2013.01); G06F 1/3228 (2013.01); G06F 9/3016 (2013.01); G06F 9/3818 (2013.01); G06F 9/52 (2013.01); G06F 11/3055 (2013.01); G06F 12/084 (2013.01); G06F 12/0831 (2013.01); G06F 12/0842 (2013.01); G06F 12/0804 (2013.01); G06F 12/0808 (2013.01); G06F 2201/885 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1028 (2013.01);
Abstract
A processor core includes a decode circuit to decode an instruction. The processor core further includes a monitor circuit, where the monitor circuit includes a data structure to store a plurality of entries for addresses that are being monitored by the monitor circuit and a triggered queue to store a plurality of addresses for which a triggering event occurred. The processor core further includes an execution circuit to execute the decoded instruction to dequeue an address from the triggered queue and return the dequeued address in response to a determination that the triggered queue is not empty.