The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2019

Filed:

Aug. 23, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Gilbert Neiger, Portland, OR (US);

Deepak K. Gupta, Portland, OR (US);

Ravi L. Sahita, Portland, OR (US);

Barry E. Huntley, Hillsboro, OR (US);

Vedvyas Shanbhogue, Austin, TX (US);

Joseph F. Cihula, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2018.01); G06F 12/1009 (2016.01); G06F 12/1027 (2016.01);
U.S. Cl.
CPC ...
G06F 9/45558 (2013.01); G06F 12/1009 (2013.01); G06F 12/1027 (2013.01); G06F 2009/45583 (2013.01); G06F 2212/65 (2013.01); G06F 2212/68 (2013.01);
Abstract

A processor comprises a register to store a first reference to a context data structure specifying a virtual machine context, the context data structure comprising a second reference to a target array and an execution unit comprising a logic circuit to execute a virtual machine (VM) based on the virtual machine context, wherein the VM comprises a guest operating system (OS) associated with a page table comprising a first memory address mapping between a guest virtual address (GVA) space and a guest physical address (GPA) space, receive a request by the guest OS to switch from the first memory address mapping to a second memory address mapping, the request comprising an index value and a first root value, retrieve an entry, identified by the index value, from the target array, the entry comprising a second root value, and responsive to determining that the first root value matches the second root value, cause a switch from the first memory address mapping to the second memory address mapping.


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