The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2019
Filed:
May. 17, 2016
Shanghai Ic R&d Center Co., Ltd., Shanghai, CN;
Rendong Huang, Shanghai, CN;
Min Zhong, Shanghai, CN;
SHANGHAI IC R&D CENTER CO., LTD, Shanghai, CN;
Abstract
A manufacturing method for gate-all-around structures in semiconductor IC manufacturing field includes forming a buried gate layer on the semiconductor substrate, forming an epitaxial layer in non-buried-gate-layer regions and planarizing the epitaxial layer so that the top surface of the epitaxial layer is at the same level with the top surface of the buried gate layer; forming a fin structure on the buried gate layer; forming a gate structure traversing and surrounding the fin structure. Since the gate structure wraps around four sides of the fin to effectively control the channel, the channel width is increased compared with the double-gate or triple gate structure, thereby increasing the effective area of the channel. The present invention solves the conventional problems like complex process and high cost without degrading the device performance. It has the advantages of simplicity, compatibility with the traditional IC planar process, low cost, and easy implementation.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile