The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2019
Filed:
Sep. 05, 2017
Applicant:
Infineon Technologies Austria Ag, Villach, AT;
Inventors:
Gerhard Prechtl, Rosegg, AT;
Horst Schäfer, Landsberg am Lech, DE;
Oliver Häberlen, St. Magdalen, AT;
Assignee:
Infineon Technologies Austria AG, Villach, AT;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 29/15 (2006.01); H01L 21/02 (2006.01); H01L 29/20 (2006.01); H01L 29/207 (2006.01); H01L 33/12 (2010.01); H01L 33/32 (2010.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/154 (2013.01); H01L 21/0254 (2013.01); H01L 21/02458 (2013.01); H01L 21/02507 (2013.01); H01L 21/02579 (2013.01); H01L 29/2003 (2013.01); H01L 29/207 (2013.01); H01L 29/7783 (2013.01); H01L 29/7784 (2013.01); H01L 29/7786 (2013.01); H01L 29/1066 (2013.01); H01L 33/12 (2013.01); H01L 33/32 (2013.01);
Abstract
In an embodiment, a method includes forming an intentionally doped superlattice laminate on a support substrate, forming a Group III nitride-based device having a heterojunction on the superlattice laminate layer, and forming a charge blocking layer between the heterojunction and the superlattice laminate.