The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2019

Filed:

Oct. 25, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Erdem Kaltalioglu, Newburgh, NY (US);

Ping-Chuan Wang, Hopewell Junction, NY (US);

Ronald Gene Filippi, Jr., Wappingers Falls, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 21/308 (2006.01); H01L 21/60 (2006.01);
U.S. Cl.
CPC ...
H01L 24/05 (2013.01); H01L 21/3081 (2013.01); H01L 23/481 (2013.01); H01L 24/03 (2013.01); H01L 24/08 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 2021/60022 (2013.01); H01L 2224/0556 (2013.01); H01L 2224/05541 (2013.01);
Abstract

The present disclosure relates generally to flip chip technology and more particularly, to a method for fabricating a mechanically anchored controlled collapse chip connection (C4) pad on a semiconductor structure and a structure formed thereby. In an embodiment, a method is disclosed that includes forming a C4 pad on a patterned dielectric layer having grooves therein, the grooves providing an interfacial surface area between the patterned dielectric layer and the C4 pad sufficient to inhibit the C4 pad from delaminating during thermal expansion or contraction.


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