The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2019

Filed:

May. 24, 2018
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

He Ren, San Jose, CA (US);

Minrui Yu, Sunnyvale, CA (US);

Mehul B. Naik, San Jose, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/40 (2006.01); H01L 21/285 (2006.01); H01L 21/67 (2006.01); H01L 23/532 (2006.01); H01L 21/768 (2006.01); C23C 14/06 (2006.01); C23C 14/34 (2006.01); C23C 14/35 (2006.01); H01J 37/34 (2006.01);
U.S. Cl.
CPC ...
H01L 21/2855 (2013.01); C23C 14/0682 (2013.01); C23C 14/3464 (2013.01); C23C 14/352 (2013.01); H01J 37/3417 (2013.01); H01J 37/3429 (2013.01); H01J 37/3435 (2013.01); H01J 37/3447 (2013.01); H01L 21/67138 (2013.01); H01L 21/76877 (2013.01); H01L 23/53209 (2013.01);
Abstract

Methods for depositing a low resistivity nickel silicide layer used in forming an interconnect and electronic devices formed using the methods are described herein. In one embodiment, a method for depositing a layer includes positioning a substrate on a substrate support in a processing chamber, the processing chamber having a nickel target and a silicon target disposed therein, the substrate facing portions of the nickel target and the silicon target each having an angle of between about 10 degrees and about 50 degrees from the target facing surface of the substrate, flowing a gas into the processing chamber, applying an RF power to the nickel target and concurrently applying a DC power to the silicon target, concurrently sputtering silicon and nickel from the silicon and nickel targets, respectively, and depositing a NiSilayer on the substrate, where x is between about 0.01 and about 0.99.


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