The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2019

Filed:

Oct. 31, 2017
Applicant:

Seagate Technology Llc, Cupertino, CA (US);

Inventors:

Ludovic Danjean, San Jose, CA (US);

Sundararajan Sankaranarayanan, Fremont, CA (US);

Erich F. Haratsch, San Jose, CA (US);

Assignee:

Seagate Technology LLC, Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/56 (2006.01); G11C 16/22 (2006.01);
U.S. Cl.
CPC ...
G11C 11/5642 (2013.01); G11C 11/5635 (2013.01); G11C 16/22 (2013.01);
Abstract

Adaptive read reference voltage tracking techniques are provided that employ charge leakage mitigation. An exemplary device for use with multi-level memory cells, comprises a controller configured to: after a predefined time interval that approximates a settling time after a programming of the multi-level memory cells until a charge leakage of one or more of the multi-level memory cells has settled, determine a plurality of read reference voltages for the multi-level memory cells using a post-programming adaptive tracking algorithm; and employ the plurality of read reference voltages to read data from the multi-level memory cells. The reference voltage offsets are optionally determined based on a shift in the read reference voltages after the predefined time interval since the programming of the multi-level memory cells.


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