The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2019

Filed:

Mar. 27, 2018
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Hernan A. Castro, Shingle Springs, CA (US);

Kerry Dean Tedrow, Folsom, CA (US);

Jack Chinho Wu, San Jose, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G11C 8/10 (2006.01); G11C 8/12 (2006.01); G11C 13/00 (2006.01); G06F 12/06 (2006.01); G06F 3/06 (2006.01); G06F 13/40 (2006.01); G11C 5/02 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1605 (2013.01); G06F 3/0604 (2013.01); G06F 3/0635 (2013.01); G06F 3/0683 (2013.01); G06F 12/0653 (2013.01); G06F 13/1668 (2013.01); G06F 13/4022 (2013.01); G11C 8/10 (2013.01); G11C 8/12 (2013.01); G11C 13/0023 (2013.01); G11C 13/0033 (2013.01); G06F 2212/1008 (2013.01); G06F 2212/1041 (2013.01); G11C 5/025 (2013.01); G11C 2213/71 (2013.01);
Abstract

In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.


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