The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2019

Filed:

Aug. 15, 2017
Applicant:

Stmicroelectronics International N.v., Schiphol, NL;

Inventors:

Saurabh Kumar Singh, Noida, IN;

Balwant Singh, Greater Noida, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31725 (2013.01);
Abstract

A test circuit measures both the rising edge delay and the falling edge delay associated with a logic cell. The test circuit includes a flip-flop type ring oscillator with two groups of logic cells connected in series in the oscillation path. A first multiplexor switches the ring oscillator between a rising edge and a falling edge mode. A second multiplexer causes the second group of logic cells to be included or excluded from the oscillation path. By measuring the oscillation period in the various modes, the rising edge and falling edge delays can be individually calculated.


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