The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2019

Filed:

Sep. 07, 2015
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Yoshikuni Miyata, Tokyo, JP;

Kenya Sugihara, Tokyo, JP;

Hideo Yoshida, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); H04L 1/00 (2006.01); H03M 13/27 (2006.01); H04J 3/16 (2006.01);
U.S. Cl.
CPC ...
H04L 1/0071 (2013.01); H03M 13/2703 (2013.01); H03M 13/2792 (2013.01); H03M 13/2796 (2013.01); H03M 13/6508 (2013.01); H03M 13/6561 (2013.01); H03M 13/6563 (2013.01); H04L 1/0041 (2013.01); H04J 3/1652 (2013.01); H04J 2203/0089 (2013.01);
Abstract

An error correction encoder () includes an interleaver circuit (), encoding circuits () and a deinterleaver circuit (). The interleaver circuit () generates, in a standard speed mode, a single series of yet-to-be-coded bit sequences (IL) on the basis of the bits in plural columns that are arranged at an interval of C columns in a single series of transmission frames, and generates, in a two-times speed mode, two series of yet-to-be-coded bit sequences (IL, IL) on the basis of the bits in plural columns that are arranged at an interval of C/2 columns in each of two series of transmission frames. The encoding circuits () apply error-correction coding to either the single series of yet-to-be-coded bit sequences (IL) or the two series of yet-to-be-coded bit sequences (IL, IL).


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