The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2019

Filed:

Jul. 17, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Takashi Ando, Tuckahoe, NY (US);

Michael Rizzolo, Albany, NY (US);

Lawrence A. Clevenger, Saratoga Springs, NY (US);

Shyng-Tsong Chen, Rensselaer, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); H01L 27/24 (2006.01); G06N 3/04 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1675 (2013.01); G06N 3/04 (2013.01); H01L 27/2463 (2013.01); H01L 45/08 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/146 (2013.01);
Abstract

A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a RRAM stack including a bottom electrode, a top electrode, and a bi-layer hardmask, forming a low-k dielectric layer over the RRAM stack, removing a first layer of the bi-layer hardmask during a via opening, and removing a second layer of the bilayer hardmask concurrently with a plurality of sacrificial layers formed over the low-k dielectric layer.


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