The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 2019
Filed:
Sep. 20, 2017
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventors:
Sun-Ha Hwang, Gyeonggi-do, KR;
Pyong-Su Kwag, Chungcheongbuk-do, KR;
Sang-Uk Park, Chungcheongbuk-do, KR;
Kwang-Deok Kim, Gyeonggi-do, KR;
Ho-Ryeong Lee, Gyeonggi-do, KR;
Ju-Tae Ryu, Gyeonggi-do, KR;
Assignee:
SK hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/94 (2006.01); H01L 27/146 (2006.01); H01L 49/02 (2006.01); H01L 23/522 (2006.01); H01L 27/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/94 (2013.01); H01L 27/14614 (2013.01); H01L 28/60 (2013.01); H01L 28/86 (2013.01); H01L 23/5223 (2013.01); H01L 27/0805 (2013.01);
Abstract
A MOS capacitor may include: an isolation layer formed in a substrate and defining an active region; a first electrode formed in the active region, and including an impurity region spaced from the isolation layer; and a second electrode formed over the substrate overlapping the impurity region, and including a gate having a plurality of gate patterns adjacent to each other with a gap therebetween.