The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2019

Filed:

Mar. 30, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

John B. Campi, Jr., Westford, VT (US);

Robert J. Gauthier, Jr., Hinesburg, VT (US);

Rahul Mishra, Essex Junction, VT (US);

Souvick Mitra, Essex Junction, VT (US);

Mujahid Muhammad, Essex Junction, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); B29C 48/21 (2019.01); B29C 48/49 (2019.01); H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01); B29C 37/00 (2006.01); B32B 3/08 (2006.01); B32B 7/02 (2019.01); B32B 27/00 (2006.01); B32B 27/08 (2006.01); B32B 27/28 (2006.01); B32B 27/30 (2006.01); B32B 27/32 (2006.01); B32B 27/34 (2006.01); B32B 27/36 (2006.01); H01G 4/005 (2006.01); H01G 4/14 (2006.01); H01G 4/228 (2006.01); H01G 4/30 (2006.01); H01G 4/33 (2006.01); H01L 21/8234 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 27/088 (2006.01); B29K 23/00 (2006.01); B29K 105/16 (2006.01); B29K 507/04 (2006.01); B29L 9/00 (2006.01); B29L 31/34 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7856 (2013.01); B29C 37/0025 (2013.01); B29C 48/21 (2019.02); B29C 48/49 (2019.02); B32B 3/08 (2013.01); B32B 7/02 (2013.01); B32B 27/00 (2013.01); B32B 27/08 (2013.01); B32B 27/28 (2013.01); B32B 27/306 (2013.01); B32B 27/308 (2013.01); B32B 27/32 (2013.01); B32B 27/34 (2013.01); B32B 27/36 (2013.01); H01G 4/005 (2013.01); H01G 4/14 (2013.01); H01G 4/228 (2013.01); H01G 4/30 (2013.01); H01G 4/33 (2013.01); H01L 21/266 (2013.01); H01L 21/26513 (2013.01); H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 21/823475 (2013.01); H01L 21/823481 (2013.01); H01L 21/823493 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/0653 (2013.01); H01L 29/0657 (2013.01); H01L 29/0696 (2013.01); H01L 29/086 (2013.01); H01L 29/0865 (2013.01); H01L 29/0869 (2013.01); H01L 29/0882 (2013.01); H01L 29/0886 (2013.01); H01L 29/1045 (2013.01); H01L 29/1095 (2013.01); H01L 29/4236 (2013.01); H01L 29/4238 (2013.01); H01L 29/42376 (2013.01); H01L 29/42392 (2013.01); H01L 29/66681 (2013.01); H01L 29/66704 (2013.01); H01L 29/66712 (2013.01); H01L 29/66734 (2013.01); H01L 29/66795 (2013.01); H01L 29/7802 (2013.01); H01L 29/7809 (2013.01); H01L 29/7811 (2013.01); H01L 29/7816 (2013.01); H01L 29/7825 (2013.01); H01L 29/7851 (2013.01); B29K 2023/12 (2013.01); B29K 2105/16 (2013.01); B29K 2507/04 (2013.01); B29K 2995/0005 (2013.01); B29K 2995/0007 (2013.01); B29L 2009/003 (2013.01); B29L 2009/005 (2013.01); B29L 2031/34 (2013.01); B32B 2262/106 (2013.01); B32B 2264/105 (2013.01); B32B 2264/12 (2013.01); B32B 2270/00 (2013.01); B32B 2274/00 (2013.01); B32B 2307/202 (2013.01); B32B 2307/204 (2013.01); B32B 2307/206 (2013.01); B32B 2307/518 (2013.01); B32B 2307/732 (2013.01); B32B 2457/16 (2013.01); H01L 2029/7858 (2013.01);
Abstract

A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.


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