The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2019

Filed:

Nov. 25, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Andrew M. Greene, Albany, NY (US);

Balasubramanian P. Haran, Albany, NY (US);

Injo Ok, Loudonville, NY (US);

Charan V. Surisetty, Clifton Park, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 21/28 (2006.01); H01L 21/3213 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/28079 (2013.01); H01L 21/3213 (2013.01); H01L 21/823431 (2013.01); H01L 21/823821 (2013.01); H01L 27/0886 (2013.01); H01L 27/0924 (2013.01); H01L 29/0649 (2013.01); H01L 29/4238 (2013.01); H01L 29/42376 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7855 (2013.01); H01L 29/7856 (2013.01); H01L 21/82345 (2013.01); H01L 21/823828 (2013.01); H01L 2029/7858 (2013.01);
Abstract

A technique relates to forming a semiconductor device. A starting semiconductor device having a fin structure patterned in a substrate, and a gate formed over the fin structure, the gate having a mid-region and an end-region is first provided. A trench is then patterned over the mid-region of the gate and a trench is patterned over the end-region of the gate. The patterned trenches are then etched over the mid-region of the gate and the end-region of the gate to form the trenches. A conformal low-k dielectric layer can then be deposited over the structure to fill the trenches and pinch off the trench formed in the mid-region and the trench formed in the end-region.


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