The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2019

Filed:

Jan. 11, 2018
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Chung-Hsien Liu, Taichung, TW;

Chun-Hsu Chen, Taichung, TW;

Lu-Ping Chiang, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 29/51 (2006.01); H01L 21/311 (2006.01); H01L 29/49 (2006.01); H01L 27/11521 (2017.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42324 (2013.01); H01L 21/0214 (2013.01); H01L 21/0217 (2013.01); H01L 21/02359 (2013.01); H01L 21/28273 (2013.01); H01L 21/31111 (2013.01); H01L 27/11521 (2013.01); H01L 29/4916 (2013.01); H01L 29/518 (2013.01); H01L 21/02247 (2013.01); H01L 21/02252 (2013.01); H01L 21/02271 (2013.01); H01L 21/02345 (2013.01); H01L 21/76224 (2013.01);
Abstract

A method of manufacturing a memory device including following steps is provided. A first dielectric layer and a first conductive layer are formed in order on the substrate. A first opening and a second opening on the first opening are formed in the substrate, the first dielectric layer and the first conductive layer. An isolation structure is formed in the first opening. A second dielectric layer is formed on the substrate to conformally cover a top surface of the first conductive layer and a surface of the second opening. A heat treatment is performed on the second dielectric layer to enhance the bonding between the second dielectric layer and the first conductive layer. An etching process is performed, so as to remove a portion of the second dielectric layer and expose a top surface of the isolation structure.


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