The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2019

Filed:

May. 27, 2016
Applicant:

Floadia Corporation, Kodaira-shi, Tokyo, JP;

Inventors:

Yasuhiro Taniguchi, Kodaira, JP;

Fukuo Owada, Kodaira, JP;

Yasuhiko Kawashima, Kodaira, JP;

Shinji Yoshida, Kodaira, JP;

Kosuke Okuyama, Kodaira, JP;

Assignee:

FLOADIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11568 (2017.01); H01L 29/40 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01); H01L 27/115 (2017.01); H01L 29/423 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/408 (2013.01); H01L 27/115 (2013.01); H01L 27/11568 (2013.01); H01L 29/42344 (2013.01); H01L 29/788 (2013.01); H01L 29/792 (2013.01); G11C 16/0466 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); H01L 29/401 (2013.01); H01L 29/66833 (2013.01);
Abstract

A memory cell and a non-volatile semiconductor memory device are disclosed. Nitride sidewall layers are respectively disposed in a first sidewall spacer and a second sidewall spacer, to separate a memory gate electrode and a first select gate electrode from each other and the memory gate electrode and a second select gate electrode from each other. Hence, a breakdown voltage is improved around the memory gate electrode as compared with a conventional case in which the first sidewall spacer and the second sidewall spacer are simply made of insulating oxide films. The nitride sidewall layers are disposed farther from a memory well than a charge storage layer. Hence, charge is unlikely to be injected into the nitride sidewall layers at charge injection from the memory well into the charge storage layer, thereby preventing an operation failure due to charge storage in a region other than the charge storage layer.


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