The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 2019
Filed:
May. 23, 2018
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Wei Cheng Wu, Zhubei, TW;
Jui-Tsung Lien, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MAUFACTURING CO., LTD., Hsinchu, TW;
Abstract
In a method of manufacturing a semiconductor device including a non-volatile memory formed in a memory cell area and a logic circuit formed in a peripheral area, a mask layer is formed over a substrate in the memory cell area and the peripheral area. A resist mask is formed over the peripheral area. The mask layer in the memory cell area is patterned by using the resist mask as an etching mask. The substrate is etched in the memory cell area. After etching the substrate, a memory cell structure in the memory cell area and a gate structure for the logic circuit are formed. A dielectric layer is formed to cover the memory cell structure and the gate structure. A planarization operation is performed on the dielectric layer. An upper portion of the memory cell structure is planarized during the planarization operation.