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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10381094 B1

PDFFull Text
Date of Patent:
Aug. 13, 2019

Filed:

Oct. 11, 2016

3d memory with staged-level multibit programming

Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Chen-Jun Wu, Changhua, TW;

Chih-Chang Hsieh, Hsinchu, TW;

Tzu-Hsuan Hsu, Chiayi, TW;

Hang-Ting Lue, Hsinchu, TW;

Assignee:

MACRONIX INTERNATIONAL CO., LTD., Hsinchu, TW;

Attorney:

Haynes Beffel & Wolfeld LLP

Primary Examiner:

Alexander Sofocleous

Assistant Examiner:

Alfredo Bermudez Lozada

Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/04 (2006.01); G11C 11/56 (2006.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3427 (2013.01); G11C 11/5628 (2013.01); G11C 16/0483 (2013.01); G11C 16/3413 (2013.01); G11C 16/10 (2013.01); G11C 2211/562 (2013.01); G11C 2211/5648 (2013.01);
Abstract

A two-sided, staged programming operation is applied to a memory having first and second stacks of memory cells C() and C(), i being the physical level of a cell. The staged programming operation includes applying a preliminary program stage S, an intermediate program stage S, and a final program stage Sto memory cells in the first and second stacks. In a programming order the final program stage Sis applied to memory cells in the first and second stacks at each level (i) for which the intermediate program stage Shas already been applied to the memory cells in any neighboring levels (levels i+1 and i−1). The intermediate program stage Sis applied only to memory cells for which the preliminary program stage Shas already been applied to the cells in any neighboring levels (levels i+1 and i−1).

Find Patent Forward Citations

Wu, Chen-Jun. (2019). 3d memory with staged-level multibit programming (U.S. Patent No. 10381094). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10381094

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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