The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 2019
Filed:
Mar. 19, 2018
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Adel A. Elsherbini, Chandler, AZ (US);
Javier A. Falcon, Chandler, AZ (US);
Hubert C. George, Portland, OR (US);
Shawna M. Liff, Scottsdale, AZ (US);
James S. Clarke, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 10/00 (2019.01); B82Y 10/00 (2011.01); H01L 29/12 (2006.01); H01L 23/00 (2006.01); H01L 29/66 (2006.01); H01L 25/065 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
G06N 10/00 (2019.01); B82Y 10/00 (2013.01); H01L 21/568 (2013.01); H01L 24/82 (2013.01); H01L 25/0652 (2013.01); H01L 29/127 (2013.01); H01L 29/66977 (2013.01); H01L 23/3107 (2013.01);
Abstract
Quantum computing assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a quantum computing assembly may include a plurality of dies electrically coupled to a package substrate, and lateral interconnects between different dies of the plurality of dies, wherein the lateral interconnects include a superconductor, and at least one of the dies of the plurality of dies includes quantum processing circuitry.