The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2019

Filed:

Apr. 08, 2016
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Kenneth Robert Willis, Matthews, NC (US);

Jing Wang, Shanghai, CN;

Hui Qi, Shanghai, CN;

Xuegang Zeng, Westborough, MA (US);

Zhen Mu, North Chelmsford, MA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/00 (2019.01); G01R 13/00 (2006.01); G01R 31/00 (2006.01); G06F 17/50 (2006.01); G01R 31/28 (2006.01); G01R 31/3183 (2006.01); G01R 13/02 (2006.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5036 (2013.01); G01R 31/2803 (2013.01); G01R 31/318357 (2013.01); G06F 17/5045 (2013.01); G06F 17/5081 (2013.01); G01R 13/029 (2013.01); G01R 31/2848 (2013.01); G01R 31/317 (2013.01); G06F 17/5009 (2013.01); G06F 17/5068 (2013.01); G06F 2217/02 (2013.01); G06F 2217/04 (2013.01); G06F 2217/06 (2013.01); G06F 2217/08 (2013.01); G06F 2217/16 (2013.01); G06F 2217/64 (2013.01); G06F 2217/74 (2013.01); G06F 2217/86 (2013.01);
Abstract

The present disclosure relates to a computer-implemented method for use in an electronic design. Embodiments may include receiving, using at least one processor, an electronic design and linking a printed circuit board (PCB) block to a physical layout associated with the electronic design. Embodiments may further include receiving, at a layout environment, at least one simulation parameter and performing, using a finite difference time domain ('FDTD') simulator, a time-domain simulation, based upon, at least in part, the at least one simulation parameter.


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