The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 2019
Filed:
Aug. 24, 2017
Applicant:
Via Alliance Semiconductor Co., Ltd., Shanghai, CN;
Inventors:
Huaisheng Zhang, Shanghai, CN;
Dacheng Liang, Shanghai, CN;
Boming Chen, Shanghai, CN;
Renyu Bian, Shanghai, CN;
Assignee:
VIA ALLIANCE SEMICONDUCTOR CO., LTD., Shanghai, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 15/16 (2006.01); G06F 7/57 (2006.01); G06F 7/483 (2006.01); G06F 9/38 (2018.01); G06F 7/499 (2006.01); H04N 19/85 (2014.01); G06F 7/02 (2006.01); G06F 7/74 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30014 (2013.01); G06F 7/483 (2013.01); G06F 7/57 (2013.01); G06F 9/30021 (2013.01); G06F 9/30029 (2013.01); G06F 9/30094 (2013.01); G06F 9/30185 (2013.01); G06F 9/30189 (2013.01); G06F 9/3887 (2013.01); G06F 9/3893 (2013.01); G06F 15/16 (2013.01); G06F 7/026 (2013.01); G06F 7/49936 (2013.01); G06F 7/74 (2013.01); G06F 9/30036 (2013.01); G06F 9/30134 (2013.01); G06F 2207/382 (2013.01); G06F 2207/3824 (2013.01); H04N 19/85 (2014.11);
Abstract
An apparatus for integrating arithmetic with logic operations contains at least a calculation device and a post-logic unit. The calculation device calculates source data to generate and output first destination data. The post-logic unit, coupled to the calculation device, performs a comparison operation for comparing the first destination data with 0 and outputs a comparison result.