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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10373967 B1

PDFFull Text
Date of Patent:
Aug. 06, 2019

Filed:

Dec. 07, 2016

Memory cell, nonvolatile semiconductor storage device, and method for manufacturing nonvolatile semiconductor storage device

Applicant:

Floadia Corporation, Kodaira-shi, Tokyo, JP;

Inventors:

Daisuke Okada, Kodaira, JP;

Kazumasa Yanagisawa, Kodaira, JP;

Fukuo Owada, Kodaira, JP;

Shoji Yoshida, Kodaira, JP;

Yasuhiko Kawashima, Kodaira, JP;

Shinji Yoshida, Kodaira, JP;

Yasuhiro Taniguchi, Kodaira, JP;

Kosuke Okuyama, Kodaira, JP;

Assignee:

FLOADIA CORPORATION, Tokyo, JP;

Attorney:

Pearne & Gordon LLP

Primary Examiner:

Farun Lu

Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/10 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01); H01L 27/11519 (2017.01); H01L 27/11521 (2017.01); H01L 27/11565 (2017.01); H01L 27/11568 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); G11C 16/04 (2013.01); H01L 27/11568 (2013.01); H01L 29/42344 (2013.01); H01L 29/6681 (2013.01); H01L 29/66545 (2013.01); H01L 29/785 (2013.01); H01L 29/788 (2013.01); H01L 29/792 (2013.01); G11C 16/0433 (2013.01); G11C 16/10 (2013.01); H01L 27/11519 (2013.01); H01L 27/11565 (2013.01);
Abstract

When a memory cell (MC) is downsized by reducing the distance between a drain region () and a source region () on the surface of a fin (S) with a high impurity concentration inside the fin (S), the shape of the fin (S) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.

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