The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2019

Filed:

Sep. 20, 2018
Applicant:

Oracle International Corporation, Redwood City, CA (US);

Inventors:

Stephen Lindquist, Boylston, MA (US);

William Izzicupo, Bedford, NH (US);

Lyne Dore, Chelmsford, MA (US);

Todd Ellsworth, Ashburnham, MA (US);

Daniela Buchman, Mountain View, CA (US);

Assignee:

ORACLE INTERNATIONAL CORPORATION, Redwood City, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 7/14 (2006.01); H05K 13/00 (2006.01);
U.S. Cl.
CPC ...
H05K 7/1489 (2013.01); H05K 7/1417 (2013.01); H05K 7/1439 (2013.01); H05K 7/1485 (2013.01); H05K 7/1487 (2013.01); H05K 7/1492 (2013.01); H05K 13/00 (2013.01);
Abstract

Utilities (e.g., apparatuses, systems, methods, etc.) for reducing or eliminating gaps between the tips of male pins and the bottoms of corresponding female sockets of interfaced connectors (e.g., daughtercard and backplane connectors) of a computing module and a backplane of a server enclosure under a variety of differing mechanical tolerances in the lengths of the server enclosure and the computing module (e.g., along a dimension that is parallel to the longitudinal axes of the male pins and female sockets). The disclosed utilities allow for increased signal quality and data rates through interfaced connectors while reducing strain on the PCB, solder joints, and the like during the interfacing of the connectors.


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