The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2019

Filed:

Oct. 10, 2018
Applicant:

Rambus Inc., Sunnyvale, CA (US);

Inventors:

Marko Aleksic, Mountain View, CA (US);

Simon Li, Cupertino, CA (US);

Roxanne Vu, San Jose, CA (US);

Assignee:

Rambus Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/033 (2006.01); H03L 7/081 (2006.01); H04L 7/00 (2006.01); H04L 25/03 (2006.01); H04L 25/02 (2006.01);
U.S. Cl.
CPC ...
H04L 7/033 (2013.01); H03L 7/081 (2013.01); H04L 7/0079 (2013.01); H04L 25/03 (2013.01); H04L 7/0004 (2013.01); H04L 7/0337 (2013.01); H04L 25/0292 (2013.01); H04L 2025/03802 (2013.01);
Abstract

A receiver with clock phase calibration is disclosed. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.


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