The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2019

Filed:

Sep. 08, 2017
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Hidenori Miyagawa, Yokkaichi, JP;

Riichiro Takaishi, Kawasaki, JP;

Toshinori Numata, Kamakura, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/04 (2006.01); H01L 27/11582 (2017.01); H01L 29/36 (2006.01); H01L 27/11565 (2017.01); H01L 27/11575 (2017.01);
U.S. Cl.
CPC ...
H01L 29/04 (2013.01); H01L 27/11565 (2013.01); H01L 27/11582 (2013.01); H01L 29/36 (2013.01); H01L 27/11575 (2013.01);
Abstract

A semiconductor memory device according to an embodiment comprises a plurality of control gate electrodes, a first semiconductor layer, and a gate insulating layer. The plurality of control gate electrodes are arranged in a first direction that intersects a surface of a substrate. The first semiconductor layer extends in the first direction and faces side surfaces in a second direction intersecting the first direction, of the plurality of control gate electrodes. The gate insulating layer is provided between the control gate electrode and the first semiconductor layer. In addition, the first semiconductor layer includes: a first portion having a first plane orientation; and a second portion having a second plane orientation which is different from the first plane orientation.


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