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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10367031 B1

PDFFull Text
Date of Patent:
Jul. 30, 2019

Filed:

Sep. 12, 2017

Sequential integration process

Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Amey Mahadev Walke, Heverlee, BE;

Anne Vandooren, Mazy, BE;

Nadine Collaert, Blanden, BE;

Assignee:

IMEC VZW, Leuven, BE;

Attorney:

McDonnell Boehnen Hulbert & Berghoff LLP

Primary Examiner:

Bitew A Dinke

Int. Cl.
CPC ...
H01L 23/40 (2006.01); H01L 27/148 (2006.01); H01L 21/768 (2006.01); H01L 21/822 (2006.01); H01L 27/06 (2006.01); H01L 29/417 (2006.01); H01L 31/0216 (2014.01); H01L 21/8258 (2006.01); B28D 1/00 (2006.01); H01L 21/304 (2006.01); H01L 31/0224 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14875 (2013.01); H01L 21/76898 (2013.01); H01L 21/8221 (2013.01); H01L 27/0688 (2013.01); H01L 27/0694 (2013.01); H01L 29/41708 (2013.01); H01L 31/02164 (2013.01); B28D 1/005 (2013.01); H01L 21/304 (2013.01); H01L 21/8258 (2013.01); H01L 31/022408 (2013.01);
Abstract

A sequential integration process is described. An example process involves forming a wafer stack by bonding a first wafer to a second wafer with a front side of the first wafer facing a front side of the second wafer, the first wafer including a first device region formed on the front side of the first wafer and including a set of semiconductor devices. The example process involves, subsequent to forming the wafer stack, forming a second device region on a back side of the first wafer, the second device region including a set of semiconductor devices. The example process involves forming at least one interconnection layer on the second device region for electrically interconnecting the semiconductor devices of the second device region. The example process also involves forming at least one via extending through the wafer stack from the at least one interconnection layer and through the first wafer.

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