The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2019

Filed:

Apr. 17, 2018
Applicant:

Nustorage Technology Co., Ltd., Apia, WS;

Inventors:

Fu-Chou Liu, Hsin-Chu County, TW;

Yung-Tin Chen, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/1159 (2017.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01); H01L 29/04 (2006.01); H01L 29/49 (2006.01); G11C 11/22 (2006.01); H01L 27/11597 (2017.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 21/266 (2006.01); H01L 21/265 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1159 (2013.01); G11C 11/223 (2013.01); G11C 11/2273 (2013.01); G11C 11/2275 (2013.01); H01L 27/11597 (2013.01); H01L 29/04 (2013.01); H01L 29/4966 (2013.01); H01L 29/513 (2013.01); H01L 29/516 (2013.01); H01L 29/517 (2013.01); H01L 29/6675 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09); H01L 29/78642 (2013.01); H01L 21/02181 (2013.01); H01L 21/02189 (2013.01); H01L 21/02194 (2013.01); H01L 21/266 (2013.01); H01L 21/26513 (2013.01); H01L 21/28088 (2013.01); H01L 21/28291 (2013.01);
Abstract

A vertical ferroelectric thin film storage transistor and a data write and read method thereof are disclosed. The vertical ferroelectric thin film storage transistor includes a substrate having a first surface, a first conductive structure, a first insulating layer, a second conductive structure, and a second insulating layer sequentially disposed above a first surface of a substrate, and a vertical hole penetrates through the layers in a direction substantially perpendicular to the first surface of the substrate. A channel layer is disposed on a wall surface of the vertical hole and in electrical contact with the first conductive structure and the second conductive structure. An inner dielectric layer is disposed on one side of the channel layer. A ferroelectric layer is disposed on one side of the inner dielectric layer. A gate structure is disposed on one side of the ferroelectric layer. A third conductive structure is disposed above the second insulating layer or in the substrate, and in electrical contact with the third conducting structure and the gate structure.


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