The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2019

Filed:

Sep. 14, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Robert C. Wong, Poughkeepsie, NY (US);

Lei Zhuang, White Plains, NY (US);

Ananthan Raghunathan, Wappingers Falls, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 21/308 (2006.01); H01L 21/3065 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); H01L 21/3065 (2013.01); H01L 21/3085 (2013.01); H01L 21/56 (2013.01); H01L 23/3171 (2013.01); H01L 27/0207 (2013.01);
Abstract

Fabrication method for a semiconductor memory device and structure are provided, which includes: providing at least two mask layers over a pair of fin structures extended above a substrate, wherein a first mask layer of the at least two mask layers is orthogonal to a second mask layer of the at least two mask layers; and patterning the pair of fin structures to define a pass-gate transistor, wherein the first mask layer facilitates removing of a portion of a first fin structure of the pair of fin structures to define a first pass-gate fin portion of the pass-gate transistor, and the second mask layer protects a second fin structure of the pair of fin structures to define a second pass-gate fin portion of the pass-gate transistor.


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