The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2019

Filed:

Dec. 22, 2016
Applicant:

Shindengen Electric Manufacturing Co., Ltd., Chiyoda-ku, JP;

Inventors:

Ryohei Kotani, Hanno, JP;

Toshiki Matsubara, Hanno, JP;

Nobutaka Ishizuka, Hanno, JP;

Masato Mikawa, Hanno, JP;

Hiroshi Oshino, Hanno, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/866 (2006.01); H01L 27/02 (2006.01); H01L 29/06 (2006.01); H03K 17/081 (2006.01); H01L 29/739 (2006.01); H01L 29/36 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0255 (2013.01); H01L 29/0688 (2013.01); H01L 29/0692 (2013.01); H01L 29/36 (2013.01); H01L 29/7395 (2013.01); H01L 29/866 (2013.01); H03K 17/08116 (2013.01);
Abstract

A semiconductor switch SW that includes a collector electrode C, an emitter electrode E and a gate electrode G, a Zener diodeA configured to include one end electrically connected to the collector electrode C, the other end electrically connected to the gate electrode G, and n-type semiconductor layers and p-type semiconductor layers alternately arranged adjacent to each other, a Zener diodeB configured to include one end electrically connected to the gate electrode G, the other end electrically connected to the emitter electrode E, and n-type semiconductor layers and p-type semiconductor layers alternately arranged adjacent to each other, are provided. The Zener diodeA and the Zener diodeB are configured so as not to allow the voltage of the gate electrode G to be increased to an on-threshold voltage of the semiconductor switch SW in the reverse bias application state.


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