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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10366884 B1

PDFFull Text
Date of Patent:
Jul. 30, 2019

Filed:

Nov. 08, 2018

Methods for forming a germanium island using selective epitaxial growth and a sacrificial filling layer

Applicant:

Stratio, Seoul, KR;

Inventors:

Jaehyung Lee, Palo Alto, CA (US);

Yeul Na, East Palo Alto, CA (US);

Youngsik Kim, Seoul, KR;

Assignee:

STRATIO, Seoul, KR;

Attorney:

Morgan, Lewis & Bockius LLP

Primary Examiner:

Shaun M Campbell

Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/3105 (2006.01); H01L 21/8238 (2006.01); H01L 23/532 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02636 (2013.01); H01L 21/02532 (2013.01); H01L 21/02664 (2013.01); H01L 21/30625 (2013.01); H01L 21/31053 (2013.01); H01L 21/823871 (2013.01); H01L 21/823892 (2013.01); H01L 23/53271 (2013.01); H01L 27/092 (2013.01); H01L 21/02381 (2013.01); H01L 21/02488 (2013.01);
Abstract

A method for obtaining a semiconductor island includes epitaxially growing a semiconductor structure over a substrate with a mask layer defining a region not covered by the mask layer. The semiconductor structure includes a first portion located adjacent to the mask layer and a second portion located away from the mask layer. The first portion has a first height that is less than a second height of a portion of the mask layer located adjacent to the first portion. The second portion has a third height that is equal to, or greater than, the second height. The method also includes forming a filling layer over at least the first portion; and, subsequently removing at least a portion of the semiconductor structure that is located above the second height. Devices made by this method are also disclosed.

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