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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10366771 B1

PDFFull Text
Date of Patent:
Jul. 30, 2019

Filed:

Sep. 13, 2017

Controller, memory system, and block management method for nand flash memory using the same

Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Kazutaka Takizawa, Yokohama, JP;

Masaaki Niijima, Machida, JP;

Assignee:

Toshiba Memory Corporation, Minato-ku, JP;

Attorney:

Oblon, McClelland, Maier & Neustadt, L.L.P.

Primary Examiner:

Mushfique Siddique

Int. Cl.
CPC ...
G11C 16/34 (2006.01); G06F 11/30 (2006.01); G06F 12/02 (2006.01); G06F 16/18 (2019.01); G11C 16/10 (2006.01); G11C 16/16 (2006.01); G11C 16/32 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3495 (2013.01); G06F 11/3037 (2013.01); G06F 11/3055 (2013.01); G06F 12/0246 (2013.01); G06F 16/1847 (2019.01); G11C 16/10 (2013.01); G11C 16/16 (2013.01); G11C 16/32 (2013.01); G06F 2212/7211 (2013.01);
Abstract

Aspects of the present disclosure include a memory system monitors at least one of an erasing time length and a programming time length of each of physical blocks included in a first logical block among a plurality of logical blocks. The memory system disassembles the first logical block among the plurality of logical blocks when both of a first physical block and a second physical block exist in the first logical block, the first physical block having an erasing time length or a programming time length falling within a first range, and the second physical block having an erasing time length or a programming time length falling outside the first range.

Find Patent Forward Citations

Takizawa, Kazutaka. (2019). Controller, memory system, and block management method for nand flash memory using the same (U.S. Patent No. 10366771). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10366771

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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