The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 30, 2019
Filed:
Jun. 26, 2017
Intel Corporation, Santa Clara, CA (US);
Eric J. Dahlen, Sherwood, OR (US);
Glenn J. Hinton, Portland, OR (US);
Raj K. Ramanujan, Federal Way, WA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes 'near memory' comprising memory made of volatile memory, and 'far memory' comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. The far memory is presented as 'main memory' to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.