The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 23, 2019
Filed:
Jun. 12, 2018
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Chenchu Punnarao Bandi, Bangalore, IN;
Amit Kumar Srivastava, Folsom, CA (US);
Navindra Navaratnam, Ipoh, MY;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/10 (2006.01); H03L 7/00 (2006.01); H03L 7/081 (2006.01); H03K 3/84 (2006.01); G06F 1/12 (2006.01);
U.S. Cl.
CPC ...
H03L 7/00 (2013.01); G06F 1/10 (2013.01); G06F 1/12 (2013.01); H03K 3/84 (2013.01); H03L 7/0818 (2013.01);
Abstract
An apparatus is provided which comprises: a receiver to receive a differential clock; a delay locked loop (DLL) coupled to the receiver; a first phase interpolator (PI) coupled to the DLL, the first PI to provide a first clock phase; a second PI coupled to the DLL, wherein the second PI is to provide a second or third clock phase; circuitry to adjust the first and second PIs according to the first clock phase, and the second or third clock phase.