The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2019

Filed:

Jul. 04, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Baek Ki, Yongin-si, KR;

Tark-Hyun Ko, Cheonan-si, KR;

Kun-Dae Yeom, Asan-si, KR;

Yong-Kwan Lee, Hwaseong-si, KR;

Keun-Ho Jang, Asan-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Yeongton-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/10 (2006.01); H01L 23/00 (2006.01); H01L 23/057 (2006.01); H01L 23/13 (2006.01); H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 23/10 (2013.01); H01L 21/565 (2013.01); H01L 23/057 (2013.01); H01L 23/13 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 24/16 (2013.01); H01L 21/561 (2013.01); H01L 23/3128 (2013.01); H01L 2224/16227 (2013.01);
Abstract

A semiconductor package includes a package substrate including at least one through-hole in a chip mounting region, a plurality of wiring patterns at a top surface of the package substrate. The wiring patterns include respective extension portions and respective landing pads. At least some of the landing pads obliquely extend toward the through-hole. Conductive bumps are formed on corresponding landing pads to connect to a semiconductor chip mounted on the chip mounting region of the package substrate. A molding material extends between the top surface of the package substrate and the semiconductor chip and fills the through-hole.


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