The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2019

Filed:

Dec. 12, 2017
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Xiankun Jin, Austin, TX (US);

Douglas A. Garrity, Gilbert, AZ (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/27 (2006.01); G01R 31/317 (2006.01); G01R 31/3177 (2006.01); G01R 31/3187 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31724 (2013.01); G01R 31/3177 (2013.01); G01R 31/31703 (2013.01);
Abstract

An on-chip built-in self-test (BIST) circuit () uses a controller (), analog-to-digital converter (ADC) (), and digital-to-analog converter (DAC) () to sense voltage and/or temperature measures at predetermined circuit locations (), to detect one or more idle states for an analog block during normal operation, to initiate a built-in self-test of the analog block during the idle state(s) by sending input test signals over a first bus () to the analog block, and to process analog test signals received over a second bus () from the analog block to generate digital built-in self-test results for the analog block so that the performance analyzer can analyze the digital built-in self-test results in combination with any voltage and/or temperature measurements to evaluate selected performance measures for the analog block against one or more performance criteria.


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