The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

Jun. 14, 2018
Applicant:

Unimicron Technology Corp., Taoyuan, TW;

Inventors:

Ming-Hao Wu, Taoyuan, TW;

Wen-Fang Liu, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 3/00 (2006.01); H01L 21/32 (2006.01); H01L 23/48 (2006.01); H05K 3/46 (2006.01); H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
H05K 1/111 (2013.01); H05K 1/115 (2013.01); H05K 3/0044 (2013.01); H05K 3/4697 (2013.01); H05K 3/3452 (2013.01); H05K 2201/0376 (2013.01); H05K 2203/025 (2013.01); H05K 2203/0228 (2013.01);
Abstract

A manufacturing method of a circuit board structure includes the following steps: providing an inner circuit structure which includes a core layer; performing a build-up process to laminate a first build-up circuit structure on a first patterned circuit layer of the inner circuit structure, wherein the first build-up circuit structure includes an inner dielectric layer, and the inner dielectric layer directly covers an upper surface of the core layer and the first patterned circuit layer; removing a portion of the first build-up circuit structure to form an opening extending from a first surface of the first build-up circuit structure relatively far away from the inner circuit structure to a portion of the inner dielectric layer; performing a sandblasting process on a first inner surface of the inner dielectric layer exposed by the opening to at least remove the portion of the inner dielectric layer exposed by the opening.


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