The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

May. 22, 2017
Applicant:

Intel Ip Corporation, Santa Clara, CA (US);

Inventors:

Steffen Reinhardt, Nuremberg, DE;

Peter Bode, Munich, DE;

Assignee:

Intel IP Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04W 56/00 (2009.01); H03M 1/00 (2006.01); H04L 12/18 (2006.01); H04W 4/10 (2009.01); H04W 24/02 (2009.01);
U.S. Cl.
CPC ...
H04W 56/001 (2013.01); H03M 1/001 (2013.01); H04L 12/189 (2013.01); H04W 4/10 (2013.01); H04W 24/02 (2013.01); H04W 56/003 (2013.01); H04W 56/005 (2013.01); H04W 56/0035 (2013.01); H04W 56/0055 (2013.01);
Abstract

A circuit arrangement may include an analog-to-digital-converter (ADC) configured to convert an analog signal into a digitized signal having an ADC frequency, a decimation circuit configured to provide a first signal having a sampling frequency based on the digitized radio signal having the ADC frequency. The sampling frequency is smaller than the ADC frequency. The circuit arrangement may further include a timer circuit providing a second signal having a timer frequency and a timing control signal to control the timing of the decimation circuit, and a difference determination circuit configured to determine a phase difference between the second signal and the first signal.


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