The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

Dec. 15, 2017
Applicant:

Atomera Incorporated, Los Gatos, CA (US);

Inventors:

Yi-Ann Chen, Campbell, CA (US);

Abid Husain, San Jose, CA (US);

Hideki Takeuchi, San Jose, CA (US);

Assignee:

ATOMERA INCORPORATED, Los Gatos, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 31/0352 (2006.01); H01L 31/109 (2006.01); H01L 31/18 (2006.01);
U.S. Cl.
CPC ...
H01L 31/035254 (2013.01); H01L 27/1461 (2013.01); H01L 27/1463 (2013.01); H01L 27/14621 (2013.01); H01L 27/14627 (2013.01); H01L 27/14645 (2013.01); H01L 27/14685 (2013.01); H01L 27/14692 (2013.01); H01L 31/109 (2013.01); H01L 31/1804 (2013.01);
Abstract

A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a plurality of laterally adjacent photodiodes formed in the substrate. Each photodiode may include a retrograde well extending downward into the substrate from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the second conductivity type, and a second well within the retrograde well having the first conductivity type. Each photodiode may further include first and second superlattices respectively overlying each of the first and second wells. Each of the first and second superlattices may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.


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