The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 16, 2019
Filed:
Aug. 31, 2015
Fuji Electric Co., Ltd., Kawasaki-shi, JP;
Takashi Saito, Matsumoto, JP;
Masaaki Ogino, Matsumoto, JP;
Eiji Mochizuki, Matsumoto, JP;
Yoshikazu Takahashi, Matsumoto, JP;
FUJI ELECTRIC CO., LTD., Kawasaki-Shi, JP;
Abstract
A MOS gate structure including a p base region, a p epitaxial layer, an nsource region, a pcontact region, an n inversion region, a gate insulating film, and a gate electrode and a front surface electrode are provided on the front surface of an epitaxial substrate obtained by depositing an nepitaxial layer on the front surface of a SiC substrate. A first metal film is provided on the front surface electrode so as to cover 10% or more, preferably, 60% to 90%, of an entire upper surface of the front surface electrode. The SiC-MOSFET is manufactured by forming a rear surface electrode, forming the first metal film on the surface of the front surface electrode, and annealing in a Natmosphere. According to this structure, it is possible to suppress a reduction in gate threshold voltage in a semiconductor device using a SiC semiconductor.