The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

Jun. 26, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Uygar E. Avci, Portland, OR (US);

Daniel H. Morris, Hillsboro, OR (US);

Ian A. Young, Portland, OR (US);

Stephen M. Ramey, North Plains, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11521 (2017.01); G11C 16/04 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01); H01L 29/788 (2006.01); H01L 27/11519 (2017.01); H01L 27/11558 (2017.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); H01L 27/11526 (2017.01); H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 27/02 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); G11C 16/0408 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); H01L 21/28079 (2013.01); H01L 21/28088 (2013.01); H01L 21/28273 (2013.01); H01L 27/11519 (2013.01); H01L 27/11526 (2013.01); H01L 27/11558 (2013.01); H01L 29/495 (2013.01); H01L 29/4916 (2013.01); H01L 29/4966 (2013.01); H01L 29/66795 (2013.01); H01L 29/66825 (2013.01); H01L 29/78 (2013.01); H01L 29/788 (2013.01); H01L 29/7851 (2013.01); H01L 29/7881 (2013.01); H01L 21/76224 (2013.01); H01L 27/0207 (2013.01); H01L 29/0649 (2013.01);
Abstract

Embodiments of the present disclosure provide techniques and configurations for semi-volatile embedded memory with between-fin floating gates. In one embodiment, an apparatus includes a semiconductor substrate and a floating-gate memory structure formed on the semiconductor substrate including a bitcell having first, second, and third fin structures extending from the substrate, an oxide layer disposed between the first and second fin structures and between the second and third fin structures, a gate of a first transistor disposed on the oxide layer and coupled with and extending over a top of the first fin structure, and a floating gate of a second transistor disposed on the oxide layer between the second and third fin structures. Other embodiments may be described and/or claimed.


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