The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

Oct. 03, 2017
Applicants:

Stmicroelectronics (Crolles 2) Sas, Crolles, FR;

Stmicroelectronics (Rousset) Sas, Rousset, FR;

Inventors:

Benoît Froment, Grenoble, FR;

Stephan Niel, Meylan, FR;

Arnaud Regnier, Les Taillades, FR;

Abderrezak Marzaki, Aix en Provence, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/762 (2006.01); H01L 21/74 (2006.01); H01L 27/08 (2006.01); H01L 49/02 (2006.01); H01C 7/12 (2006.01); H01L 21/765 (2006.01); H01L 29/8605 (2006.01); H01L 23/522 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823493 (2013.01); H01C 7/126 (2013.01); H01L 21/743 (2013.01); H01L 21/765 (2013.01); H01L 21/76224 (2013.01); H01L 21/76264 (2013.01); H01L 21/76283 (2013.01); H01L 21/76286 (2013.01); H01L 23/5228 (2013.01); H01L 27/0802 (2013.01); H01L 28/20 (2013.01); H01L 29/0649 (2013.01); H01L 29/0692 (2013.01); H01L 29/8605 (2013.01);
Abstract

An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.


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