The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

Aug. 30, 2017
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Jeng-Hwa Liao, Hsinchu, TW;

Zong-Jie Ko, Kaohsiung, TW;

Jung-Yu Shieh, Hsinchu, TW;

Ling-Wuu Yang, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 21/8234 (2006.01); H01L 21/762 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 27/11548 (2017.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823481 (2013.01); H01L 21/02164 (2013.01); H01L 21/02222 (2013.01); H01L 21/02271 (2013.01); H01L 21/02282 (2013.01); H01L 21/02356 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/76229 (2013.01); H01L 27/11548 (2013.01); H01L 29/42364 (2013.01);
Abstract

Provided is a semiconductor memory device including a substrate, a plurality of first isolation structures, and a plurality of second isolation structures. The substrate includes a periphery region and an array region. The first isolation structures are located in the substrate of the periphery region. The second isolation structures are located in the substrate of the array region. A material of the first isolation structures is different from a material of the second isolation structures. A width of each of the first isolation structures is greater than a width of each of the second isolation structures.


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