The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 16, 2019
Filed:
Nov. 01, 2017
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Nai-Chia Chen, Hsinchu, TW;
Chun-Li Chou, Jhubei, TW;
Yen-Chiu Kuo, Tainan, TW;
Chun-Hung Chao, Hsinchu, TW;
Yu-Li Cheng, Tainan, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 23/528 (2006.01); B08B 3/02 (2006.01); B08B 3/08 (2006.01); H01L 23/522 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76814 (2013.01); B08B 3/024 (2013.01); B08B 3/08 (2013.01); H01L 21/02063 (2013.01); H01L 21/76849 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 21/02101 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01);
Abstract
A method of forming a semiconductor device includes forming a conductive feature in a first dielectric layer, forming one or more dielectric layers over the first dielectric layer, and forming a via opening in the one or more dielectric layers, a bottom of the via opening exposing the conductive feature. The method further includes cleaning the via opening using a chemical mixture, and rinsing the via opening using basic-ion doped water after cleaning the via opening.