The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

Mar. 14, 2018
Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Hiroyuki Kamiya, Yokkaichi, JP;

Shigehisa Inoue, Yokkaichi, JP;

Seiji Shimabukuro, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01); G11C 13/00 (2006.01); H01L 21/8229 (2006.01); H01L 21/8238 (2006.01); H01L 21/8234 (2006.01); H01L 21/822 (2006.01); H01L 21/8232 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02211 (2013.01); G11C 13/0007 (2013.01); H01L 21/02107 (2013.01); H01L 21/02126 (2013.01); H01L 21/02164 (2013.01); H01L 21/02214 (2013.01); H01L 21/8221 (2013.01); H01L 21/8229 (2013.01); H01L 21/8232 (2013.01); H01L 21/823487 (2013.01); H01L 21/823885 (2013.01); H01L 27/249 (2013.01); H01L 45/08 (2013.01); H01L 45/124 (2013.01); H01L 45/1253 (2013.01); H01L 45/146 (2013.01); H01L 45/1683 (2013.01); G11C 2213/32 (2013.01); G11C 2213/51 (2013.01); G11C 2213/52 (2013.01); G11C 2213/71 (2013.01); G11C 2213/79 (2013.01); H01L 27/2454 (2013.01);
Abstract

An alternating stack of insulating layers including a silicon oxide material and electrically conductive layers is formed over a substrate. Sidewalls of the insulating layers are selectively silylated with a chemical including at least one silyl group without silylating sidewalls of the electrically conductive layers. Silicon-containing barrier material portions are formed by selectively growing a first silicon-containing barrier material from surfaces of the electrically conductive layers without growing the first silicon-containing barrier material from silylated surfaces of the insulating layers. A memory material layer is formed on the silicon-containing barrier material portions and the sidewalls of the insulating layers. A vertical conductive line is formed on the memory material layer.


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