The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

Jan. 31, 2017
Applicant:

Stmicroelectronics International N.v, Amsterdam, NL;

Inventors:

Swapnil Bahl, New Delhi, IN;

Shray Khullar, New Delhi, IN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/25 (2006.01); G11C 29/32 (2006.01); G01R 31/3177 (2006.01); G01R 31/3185 (2006.01); G11C 29/34 (2006.01);
U.S. Cl.
CPC ...
G11C 29/32 (2013.01); G01R 31/3177 (2013.01); G01R 31/318541 (2013.01); G01R 31/318547 (2013.01); G06F 11/25 (2013.01); G11C 29/34 (2013.01); G11C 2029/3202 (2013.01);
Abstract

An integrated circuit (IC) having a scan compression architecture includes decompression logic coupled between test access input and a block of IC elements (e.g. flip-flops) coupled together to define a plurality of scan paths. The block of IC elements includes an initial data selector at an initial position of each of the scan paths, and an additional data selector downstream within at least one of the scan paths and configured to reconfigure an order of the IC elements within the at least one scan path. Compression logic is coupled between the block of IC elements and a test access output.


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