The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 09, 2019
Filed:
Mar. 09, 2018
University of Utah Research Foundation, Salt Lake City, UT (US);
École Polytechnique Fédérale DE Lausanne, Lausanne, CH;
Pierre-Emanuel Gaillardon, Salt Lake City, UT (US);
Xifan Tang, Lausanne, CH;
Gain Kim, Lausanne, CH;
Giovanni De Micheli, Lausanne, CH;
Edouard Giacomin, Salt Lake City, UT (US);
University of Utah Research Foundation, Salt Lake City, UT (US);
Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne, CH;
Abstract
Resistive random access memory (RRAM) based multiplexers and field programmable gate arrays (FPGAs) are provided. The RRAM-based multiplexers and FPGAs include a 4T1R programming structure to program the RRAMs. The programming structure includes two programming transistors connected between the power supply and the top electrode of the RRAM and two programming transistors connected between the power supply and the bottom electrode of the RRAM. The programming transistors are used to set and rest the RRAMs. In the RRAM-based multiplexer programming transistors connected to the bottom electrodes are shared between a plurality of RRAMs. The shared programming transistors and an output inverter of the RRAM are provided in a deep N-well of the RRAM-based multiplexer. The programming transistors connected to the top electrodes of the RRAMs and a plurality of input inverters are provided in a regular well of the RRAM-based multiplexer.