The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2019

Filed:

Nov. 21, 2017
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Yu Lu, Hangzhou, CN;

Junjing Bao, San Diego, CA (US);

Xia Li, San Diego, CA (US);

Seung Hyuk Kang, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 43/02 (2006.01); H01L 23/544 (2006.01); H01L 43/08 (2006.01); H01L 43/12 (2006.01); G11C 11/16 (2006.01);
U.S. Cl.
CPC ...
H01L 43/02 (2013.01); H01L 23/544 (2013.01); H01L 43/08 (2013.01); H01L 43/12 (2013.01); G11C 11/16 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54453 (2013.01);
Abstract

A method includes patterning a photo resist layer on top of a semiconductor device. The semiconductor device includes a lower portion, a capping layer formed on top of the lower portion, and an optional oxide layer formed on top of the capping layer. The lower portion includes a dielectric material and an interconnect. The method also includes etching portions of the semiconductor device based on the photo resist layer to expose the interconnect. The method further includes depositing a bottom electrode of a resistive memory device on the interconnect. The bottom electrode is comprised of cobalt tungsten phosphorus (CoWP).


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